ECE + ML @ Virginia Tech · CPES Lab
Real-time neural inference squeezed onto FPGAs for power electronics, and diffusion models trained for electromagnetic design. I care about the millisecond where hardware meets learning.
01 · Hardware
FPGAs, power converters, sub-millisecond control loops: the layer where latency is measured in clock cycles and every design decision is real.
Selected Work
Research and products where the constraint is physical (latency budgets, LUT counts, signal noise) and the solution is intelligence built to live inside it. Each one below is explorable.
Virginia Tech · CPES Lab
A high-frequency power converter gives its controller less than a millisecond to sense, decide, and act. That budget rules out a round trip to anywhere, so the neural network moves onto each converter cell's FPGA fabric, and inference becomes just another stage in the circuit.
One fault on cell 07, two control architectures. The on-cell network answers before the centralized packet is even halfway to the hub.
In the simulation, the distributed controller finishes its fault response in 24 microseconds using an on-cell neural network. The centralized controller needs 79.2 microseconds for the same fault because the signal must travel to a central hub, queue for inference, and travel back, about 3.3 times slower.
Why locality wins: the centralized loop spends ~55 of its 79 µs on the network round-trip alone: dead time no sub-millisecond control loop can afford. Running the network on the cell deletes the trip entirely. Exact timings from the open simulation repo; the speedup is 3.3× in this run (the repo's README headline is ~4×).
The same fault-detection network, quantized to four widths, with estimated Zynq-7000 resources from the repo's FPGA estimator.
LUT usage (est.)
2,850 LUTs
The sweet spot: accuracy untouched, ~4× less area, and every DSP freed.
The takeaway: 8-bit is the sweet spot. Accuracy is nearly free (99.98% unchanged), the footprint is ~4× smaller than 32-bit, and DSP usage drops to zero. Small enough to put one detector on every cell.
Relative PL footprint, 32-bit = full frame. At 8-bit the core uses an estimated ~5.4% of a Zynq-7020's 53,200 LUTs.
<1 ms
inference target inside the control loop
~144 ns
IEEE 1588 PTP sync error across 10 cells (simulated)
99.94%
end-to-end fault-detection accuracy (simulated)
Numbers from the open simulation repo ↗: a physics-grounded simulation with first-order FPGA estimates, labeled as such.
Stanford University
A denoising diffusion model built from scratch: forward process, reverse process, and a 15.8M-parameter U-Net derived from the math, not imported from a library. The technical groundwork for DALL-EM: generative diffusion for electromagnetic design.
Start from pure Gaussian noise.
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Up Next · Assistive Tech
A surface-EMG forearm armband and ML gesture classifier driving a servo gripper for accessible prosthetics. Cross-session electrode-shift robustness is the real research problem. Targeting IEEE EMBC.
About
The first thing I built that mattered was a flashlight with no battery. Warm the plates with your hand, cool them with water, and the Seebeck effect turns that temperature difference into light. No software, no shortcuts. Just physics, made useful.
That instinct is still the center of everything I do. Today it looks like implementing neural inference directly on FPGA fabric at Virginia Tech's Center for Power Electronics Systems, where a model that can't answer in under a millisecond is a model that doesn't ship. When the constraint is physical, every design decision is real. That's where the interesting engineering lives.
I care about the full stack of physical AI: diffusion models that learn the priors of electromagnetic design, EMG signals decoded into gesture control for prosthetics, edge inference that keeps power grids stable. Intelligence is most useful when it leaves the datacenter and meets the world, and building that takes someone fluent in both the math and the metal.
I got to Virginia Tech a year early because I'd rather be building than waiting. Off the bench: evidence-based hypertrophy training (I built my own tracker because the literature deserved better software), teaching math, and cooking things that occasionally work on the first try.
Experience
Summer 2026 – Present
Virginia Tech · Center for Power Electronics Systems
Implementing edge-AI inference on FPGAs for distributed control in high-frequency power systems.
May 2026
Stanford University
Built a DDPM from scratch as the technical foundation for DALL-EM, generative diffusion for electromagnetic design.
Philosophy
01
A model that must answer in under a millisecond on resource-starved fabric can't hide behind abstraction. Hard physical budgets (latency, LUTs, watts) are where real engineering judgment gets built.
02
Before training a diffusion model, I derived the forward and reverse processes by hand. You can only adapt a method to a new domain (EM design, biosignals) if you understand why it works, not just how to call it.
03
From a battery-free flashlight to a prosthetic gripper: technology is finished when it survives contact with the physical world and makes someone more capable than they were.
Contact
I'm always open to research collaborations, hard hardware-ML problems, and conversations about where physical AI is headed.